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250 mhz, voltage output, 4-quadrant multiplier AD835 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1994C2010 analog devices, inc. all rights reserved. features simple: basic function is w = xy + z complete: minimal external components required very fast: settles to 0.1% of full scale (fs) in 20 ns dc-coupled voltage output simplifies use high differential input impedance x, y, and z inputs low multiplier noise: 50 nv/hz applications very fast multiplication, division, squaring wideband modulation and demodulation phase detection and measurement sinusoidal frequency doubling video gain control and keying voltage-controlled amplifiers and filters general description the AD835 is a complete four-quadrant, voltage output analog multiplier, fabricated on an advanced dielectrically isolated complementary bipolar process. it generates the linear product of its x and y voltage inputs with a ?3 db output bandwidth of 250 mhz (a small signal rise time of 1 ns). full-scale (?1 v to +1 v) rise to fall times are 2.5 ns (with a standard r l of 150 ), and the settling time to 0.1% under the same conditions is typically 20 ns. its differential multiplication inputs (x, y) and its summing input (z) are at high impedance. the low impedance output voltage (w) can provide up to 2.5 v and drive loads as low as 25 . normal operation is from 5 v supplies. though providing state-of-the-art speed, the AD835 is simple to use and versatile. for example, as well as permitting the addition of a signal at the output, the z input provides the means to operate the AD835 with voltage gains up to about 10. in this capacity, the very low product noise of this multiplier (50 nv/hz) makes it much more useful than earlier products. the AD835 is available in an 8-lead pdip package (n) and an 8-lead soic package (r) and is specified to operate over the ?40c to +85c industrial temperature range. functional block diagram 00883-001 x 1 x 2 x = x1 ? x2 z input y = y1 ? y2 AD835 w output y 1 y 2 xy xy + z x1 + + figure 1. product highlights 1. the AD835 is the first monolithic 250 mhz, four-quadrant voltage output multiplier. 2. minimal external components are required to apply the AD835 to a variety of signal processing applications. 3. high input impedances (100 k||2 pf) make signal source loading negligible. 4. high output current capability allows low impedance loads to be driven. 5. state-of-the-art noise levels achieved through careful device optimization and the use of a special low noise, band gap voltage reference. 6. designed to be easy to use and cost effective in applications that require the use of hybrid or board-level solutions.
AD835 rev. d | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution.................................................................................. 5 ? pin configuration and function descriptions............................. 6 ? typical performance characteristics ..............................................7 ? theory of operation ...................................................................... 10 ? basic theory ............................................................................... 10 ? scaling adjustment .................................................................... 10 ? applications information .............................................................. 11 ? multiplier connections ............................................................. 11 ? wideband voltage-controlled amplifier ............................... 11 ? amplitude modulator................................................................ 11 ? squaring and frequency doubling.......................................... 12 ? outline dimensions ....................................................................... 13 ? ordering guide .......................................................................... 14 ? revision history 12/10rev. c to rev. d changes to figure 1.......................................................................... 1 changes to absolute maximum ratings and table 2.................. 5 added figure 19, renumbered subsequent tables.................... 10 added figure 23.............................................................................. 11 10/09rev. b to rev. c updated format..................................................................universal changes to figure 22...................................................................... 11 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 14 6/03rev. a to rev. b updated format..................................................................universal updated outline dimensions ....................................................... 10
AD835 rev. d | page 3 of 16 specifications t a = 25c, v s = 5 v, r l = 150 , c l 5 pf, unless otherwise noted. table 1. parameter conditions min typ max unit transfer function ()() z u yyxx w + ? ? = 2121 input characteristics (x, y) differential voltage range v cm = 0 v 1 v differential clipping level 1.2 1 1.4 v low frequency nonlinearity x = 1 v, y = 1 v 0.3 0.5 1 % fs y = 1 v, x = 1 v 0.1 0.3 1 % fs vs. temperature t min to t max 2 x = 1 v, y = 1 v 0.7 % fs y = 1 v, x = 1 v 0.5 % fs common-mode voltage range ?2.5 +3 v offset voltage 3 20 1 mv vs. temperature t min to t max 2 25 mv cmrr f 100 khz; 1 v p-p 70 1 db bias current 10 20 1 a vs. temperature t min to t max 2 27 a offset bias current 2 a differential resistance 100 k single-sided capacitance 2 pf feedthrough, x x = 1 v, y = 0 v ?46 1 db feedthrough, y y = 1 v, x = 0 v ?60 1 db dynamic characteristics ?3 db small signal bandwidth 150 250 mhz ?0.1 db gain flatness frequency 15 mhz slew rate w = ?2.5 v to +2.5 v 1000 v/s differential gain error, x f = 3.58 mhz 0.3 % differential phase error, x f = 3.58 mhz 0.2 degrees differential gain error, y f = 3.58 mhz 0.1 % differential phase error, y f = 3.58 mhz 0.1 degrees harmonic distortion x or y = 10 dbm, second and third harmonic fund = 10 mhz ?70 db fund = 50 mhz ?40 db settling time, x or y to 0.1%, w = 2 v p-p 20 ns summing input (z) gain from z to w, f 10 mhz 0.990 0.995 ?3 db small signal bandwidth 250 mhz differential input resistance 60 k single-sided capacitance 2 pf maximum gain x, y to w, z shorted to w, f = 1 khz 50 db bias current 50 a
AD835 rev. d | page 4 of 16 parameter conditions min typ max unit output characteristics voltage swing 2.2 2.5 v vs. temperature t min to t max 2 2.0 v voltage noise spectral density x = y = 0 v, f < 10 mhz 50 nv/hz offset voltage 25 75 1 mv vs. temperature 3 t min to t max 2 10 mv short-circuit current 75 ma scale factor error 5 8 1 % fs vs. temperature t min to t max 2 9 % fs linearity (relative error) 4 0.5 1.0 1 % fs vs. temperature t min to t max 2 1.25 % fs power supplies supply voltage for specified performance 4.5 5 5.5 v quiescent supply current 16 25 1 ma vs. temperature t min to t max 2 26 ma psrr at output vs. vp +4.5 v to +5.5 v 0.5 1 %/v psrr at output vs. vn ?4.5 v to ?5.5 v 0.5 %/v 1 all minimum and maximum specifications are gua ranteed. these specifications are tested on all production units at final electr ical test. 2 t min = ?40c, t max = 85c. 3 normalized to zero at 25c. 4 linearity is defined as residual error after compensating for input offset, output voltage offset, and scale factor errors.
AD835 rev. d | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage 6 v internal power dissipation 300 mw operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature, soldering 60 sec 300c esd rating hbm 1500 v cdm 250 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for more information, see the analog devices, inc., tutor ia l mt-092, electrostatic discharge . thermal resistance table 3. package type ja jc unit 8-lead pdip (n) 90 35 c/w 8-lead soic (r) 115 45 c/w esd caution
AD835 rev. d | page 6 of 16 pin configuration and fu nction descriptions y1 1 y2 2 v n 3 z 4 x1 8 x2 7 vp 6 w 5 AD835 top view (not to scale) 00883-002 figure 2. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 y1 noninverting y multiplicand input 2 y2 inverting y multiplicand input 3 vn negative supply voltage 4 z summing input 5 w product 6 vp positive supply voltage 7 x2 inverting x multiplicand input 8 x1 noninverting x multiplicand input
AD835 rev. d | page 7 of 16 typical performance characteristics 00883-003 differential gain (%) differential phase (degrees) 0.4 0 dg dp (ntsc) field = 1 line = 18 wfm fcc composite min = 0 max = 0.2 p-p/max = 0.2 1st 2nd 3rd 4th 5th 6th 0.06 0.11 0.16 0.19 0.20 0 1st 2nd 3rd 4th 5th 6th 0.02 0.02 0.03 0.03 0.06 0.2 0 ?0.2 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 min = 0 max = 0.06 p-p = 0.06 figure 3. typical composite output differential gain and phase, ntsc for x channel; f = 3.58 mhz, r l = 150 00883-004 dg dp (ntsc) field = 1 line = 18 wfm fcc composite differential gain (%) 0.20 0 min = 0 max = 0.16 p-p = 0.16 1st 2nd 3rd 4th 5th 6th 0.03 0.04 0.07 0.10 0.16 0.10 0 ?0.10 ?0.20 differential phase (degrees) 0 1st 2nd 3rd 4th 5th 6th 0.01 0 0 ?0.01 ?0.20 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 min = ?0.02 max = 0.01 p-p/max = 0.03 figure 4. typical composite output differential gain and phase, ntsc for y channel; f = 3.58 mhz, r l = 150 00883-005 frequency (hz) gain phase magnitude (db) phase (degrees) 2 180 90 0 ?90 ?180 0 ?2 ?4 ?6 ?8 ?10 1m 10m 100m 1g x, y, z ch = 0dbm r l = 150 c l 5pf figure 5. gain and phase vs. frequency of x, y, z inputs 00883-006 frequency (hz) magnitude (db) 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 300k 10m 1m 100m 1g x, y ch = 0dbm r l = 150 c l 5pf figure 6. gain flatness to 0.1 db 00883-007 frequency (hz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 1m 10m 100m 1g x feedthrough x feedthrough y feedthrough y feedthrough x, y ch = 5dbm r l = 150 c l < 5pf figure 7. x and y feedthrough vs. frequency 00883-008 +0.2v ?0.2v gnd 100mv 10ns figure 8. small signal pulse response at w output, r l = 150 , c l 5 pf, x channel = 0.2 v, y channel = 1.0 v
AD835 rev. d | page 8 of 16 00883-009 +1v ?1v gnd 500mv 10ns figure 9. large signal pulse response at w output, r l = 150 , c l 5 pf, x channel = 1.0 v, y channel = 1.0 v 00883-010 0 20 40 60 80 1m 10m 100m cmrr (db) 1g frequency (hz) figure 10. cmrr vs. frequency for x or y channel, r l = 150 , c l 5 pf 00883-011 pssr (db) ?10 ?20 ?30 ?40 ?50 ?60 300k 1m 10m 100m 1g pssr on v? pssr on v+ 0dbm on supply x, y = 1v frequency (hz) figure 11. psrr vs. frequency for v+ and vC supply 00883-012 10db/div 10mhz 20mhz 30mhz figure 12. harmonic distortion at 10 mhz; 10 dbm input to x or y channels, r l = 150 , c l = 5 pf 00883-013 10db/div 100mhz 50mhz 150mhz figure 13. harmonic distortion at 50 mhz, 10 dbm input to x or y channel, r l = 150 , c l 5 pf 00883-014 10db/div 200mhz 100mhz 300mhz figure 14. harmonic distortion at 100 mhz, 10 dbm input to x or y channel, r l = 150 , c l 5 pf
AD835 rev. d | page 9 of 16 00883-015 10db/div +2.5v ?2.5v 10ns 1v figure 15. maximum output voltage swing, r l = 50 , c l 5 pf 00883-016 temperature ( c) v os output drift (mv) 10 15 5 0 ?5 ?10 ?15 ?55 ?35 ?15 5 25 45 65 85 105 125 output offset drift will typically be within shaded area output v os drift, normalized to 0 at 25 c figure 16. v os output drift vs. temperature 00883-017 rf frequency input to x channel (mhz) third order intercept (dbm) 30 35 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 180 200 x ch = 6dbm y ch = 10dbm r l = 100 figure 17. fixed lo on y channel vs. rf frequency input to x channel 00883-018 lo frequency on y channel (mhz) third order intercept (dbm) 30 35 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 180 200 x ch = 6dbm y ch = 10dbm r l = 100 figure 18. fixed if vs. lo frequency on y channel
AD835 rev. d | page 10 of 16 theory of operation the AD835 is a four-quadrant, voltage output analog multiplier, fabricated on an advanced dielectrically isolated complementary bipolar process. in its basic mode, it provides the linear product of its x and y voltage inputs. in this mode, the ?3 db output voltage bandwidth is 250 mhz (with small signal rise time of 1 ns). full-scale (?1 v to +1 v) rise to fall times are 2.5 ns (with a standard r l of 150 ), and the settling time to 0.1% under the same conditions is typically 20 ns. as in earlier multipliers from analog devices a unique summing feature is provided at the z input. as well as providing independent ground references for the input and the output and enhanced versatility, this feature allows the AD835 to operate with voltage gain. its x-, y-, and z-input voltages are all nominally 1 v fs, with an overrange of at least 20%. the inputs are fully differential at high impedance (100 k||2 pf) and provide a 70 db cmrr (f 1 mhz). the low impedance output is capable of driving loads as small as 25 . the peak output can be as large as 2.2 v minimum for r l = 150 , or 2.0 v minimum into r l = 50 . the AD835 has much lower noise than the ad534 or ad734 , making it attractive in low level, signal processing applications, for example, as a wideband gain control element or modulator. basic theory the multiplier is based on a classic form, having a translinear core, supported by three (x, y, and z) linearized voltage-to-current converters, and the load driving output amplifier. the scaling voltage (the denominator u in the equations) is provided by a band gap reference of novel design, optimized for ultralow noise. figure 19 shows the functional block diagram. in general terms, the AD835 provides the function ()() z u yyxx w + ?? = 2121 (1) where the variables w , u , x , y , and z are all voltages. connected as a simple multiplier, with x = x1 ? x2, y = y1 ? y2, and z = 0 and with a scale factor adjustment (see figure 19 ) that sets u = 1 v, the output can be expressed as w = xy (2) 00883-025 x 1 x 2 x = x1 ? x2 z input y = y1 ? y2 AD835 w output y 1 y 2 xy xy + z x1 + + figure 19. functional block diagram simplified representations of this sort, where all signals are presumed expressed in v, are used throughout this data sheet to avoid the needless use of less intuitive subscripted variables (such as, v x1 ). all variables as being normalized to 1 v. for example, the input x can either be stated as being in the ?1 v to +1 v range or simply C1 to +1. the latter representation is found to facilitate the development of new functions using the AD835. the explicit inclusion of the denominator, u, is also less helpful, as in the case of the AD835, if it is not an electrical input variable. scaling adjustment the basic value of u in equation 1 is nominally 1.05 v. figure 20 , which shows the basic multiplier connections, also shows how the effective value of u can be adjusted to have any lower voltage (usually 1 v) through the use of a resistive divider between w (pin 5) and z (pin 4). using the general resistor values shown, equation 1can be rewritten as () '1kw zk u xy w ?++= (3) where z ' is distinguished from the signal z at pin 4. it follows that () ' 1 z uk xy w + ? = (4) in this way, the effective value of u can be modified to u = (1 ? k ) u (5) without altering the scaling of the z' input, which is expected because the only ground reference for the output is through the z' input. therefore, to set u' to 1 v, remembering that the basic value of u is 1.05 v, r1 must have a nominal value of 20 r2. the values shown allow u to be adjusted through the nominal range of 0.95 v to 1.05 v. that is, r2 provides a 5% gain adjustment. in many applications, the exact gain of the multiplier may not be very important; in which case, this network may be omitted entirely, or r2 fixed at 100 . 00883-020 + + r1 = (1?k) r 2k r2 = kr 200 z 1 fb +5v ?5v fb AD835 4.7 f tantalum 0.01 f ceramic 0.01 f ceramic 4.7 f tantalum 1 2 3 4 8 x w y x2 vp w y1 x1 y2 vn z 7 6 5 figure 20. multiplier connections
AD835 rev. d | page 11 of 16 applications information the AD835 is easy to use and versatile. the capability for adding another signal to the output at the z input is frequently valuable. three applications of this feature are presented here: a wideband voltage-controlled amplifier, an amplitude modulator, and a frequency doubler. of course, the AD835 may also be used as a square law detector (with its x inputs and y inputs connected in parallel). in this mode, it is useful at input frequencies to well over 250 mhz because that is the bandwidth limitation of the output amplifier only. multiplier connections figure 20 shows the basic connections for multiplication. the inputs are often single sided, in which case the x2 and y2 inputs are normally grounded. note that by assigning pin 7 (x2) and pin 2 (y2), respectively, to these (inverting) inputs, an extra measure of isolation between inputs and output is provided. the x and y inputs may be reversed to achieve some desired overall sign with inputs of a particular polarity, or they may be driven fully differentially. power supply decoupling and careful board layout are always important in applying wideband circuits. the decoupling recommendations shown in figure 20 should be followed closely. in figure 21 , figure 23 , and figure 24 , these power supply decoupling components are omitted for clarity but should be used wherever optimal performance with high speed inputs is required. however, if the full, high frequency capabilities of the AD835 are not being exploited, these components can be omitted. wideband voltage-controlled amplifier figure 21 shows the AD835 configured to provide a gain of nominally 0 db to 12 db. (in fact, the control range extends from well under C12 db to about +14 db.) r1 and r2 set the gain to be nominally 4. the attendant bandwidth reduction that comes with this increased gain can be partially offset by the addition of the peaking capacitor c1. although this circuit shows the use of dual supplies, the AD835 can operate from a single 9 v supply with a slight revision. 00883-021 r1 97.6 c1 33pf r2 301 AD835 1 2 3 4 8 voltage output v g (gain control) v in (signal) x2 vp w y1 x1 y2 +5v ?5v vn z 7 6 5 figure 21. voltage-controlled 50 mhz amplifier using the AD835 the ac response of this amplifier for gains of 0 db (v g = 0.25 v), 6 db (v g = 0.5 v), and 12 db (v g = 1 v) is shown in figure 22 . in this application, the resistor values have been slightly adjusted to reflect the nominal value of u = 1.05 v. the overall sign of the gain may be controlled by the sign of v g . 00883-022 10k 100k 1m frequency (hz) ?9 ?6 ?3 0 3 6 9 12 15 18 21 gain (db) 10m 100m 12db (v g = 1v) 6db (v g = 0.5v) 0db (v g = 0.25v) figure 22. ac response of vca amplitude modulator figure 23 shows a simple modulator. the carrier is applied to the y input and the z input, while the modulating signal is applied to the x input. for zero modulation, there is no product term so the carrier input is simply replicated at unity gain by the voltage follower action from the z input. at x = 1 v, the rf output is doubled, while for x = C1 v, it is fully suppressed. that is, an x input of approximately 1 v (actually u or about 1.05 v) corresponds to a modulation index of 100%. carrier and modulation frequencies can be up to 300 mhz, somewhat beyond the nominal ?3 db bandwidth. of course, a suppressed carrier modulator can be implemented by omitting the feedforward to the z input, grounding that pin instead. 00883-026 +5v ?5v AD835 1 2 3 4 8 x2 modulation source modulated carrier output carrier source vp w y1 x1 y2 vn z 7 6 5 figure 23. simple amplitude modulator using the AD835
AD835 rev. d | page 12 of 16 squaring and frequency doubling amplitude domain squaring of an input signal, e, is achieved simply by connecting the x and y inputs in parallel to produce an output of e 2 /u. the input can have either polarity, but the output in this case is always positive. the output polarity can be reversed by interchanging either the x or y inputs. when the input is a sine wave e sin t, a signal squarer behaves as a frequency doubler because () ( t ) u e u te 2cos1 2 sin 22 ?= (6) while useful, equation 6 shows a dc term at the output, which varies strongly with the amplitude of the input, e . figure 24 shows a frequency doubler that overcomes this limitation and provides a relatively constant output over a moderately wide frequency range, determined by the time constant r1c1. the voltage applied to the x and y inputs is exactly in quadrature at a frequency f = ?c1r1, and their amplitudes are equal. at higher frequencies, the x input becomes smaller while the y input increases in amplitude; the opposite happens at lower frequencies. the result is a double frequency output centered on ground whose amplitude of 1 v for a 1 v input varies by only 0.5% over a frequency range of 10%. because there is no squared dc component at the output, sudden changes in the input amplitude do not cause a bounce in the dc level. 00883-024 AD835 1 2 3 4 8 voltage output r2 97.6 r1 r3 301 x2 vp w y1 x1 y2 +5v c1 ?5v vn z 7 6 5 v g figure 24. broadband zero -bounce frequency doubler this circuit is based on the identity =? 2sin 2 1 sincos (7) at o = 1/c1r1, the x input leads the input signal by 45 (and is attenuated by 2, while the y input lags the input signal by 45 and is also attenuated by 2. because the x and y inputs are 90 out of phase, the response of the circuit is () () ( t u e t e t e u w =+?? = 2sin 2 45sin 2 45sin 2 1 2 ) (8) which has no dc component, r2 and r3 are included to restore the output to 1 v for an input amplitude of 1 v (the same gain adjustment as previously mentioned). because the voltage across the capacitor (c1) decreases with frequency, while that across the resistor (r1) increases, the amplitude of the output varies only slightly with frequency. in fact, it is only 0.5% below its full value (at its center frequency o = 1/c1r1) at 90% and 110% of this frequency.
AD835 rev. d | page 13 of 16 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 25. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 26. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
AD835 rev. d | page 14 of 16 ordering guide model 1 temperature range package description package option AD835an ?40c to +85c 8-lead plastic dual in-line package [pdip] n-8 AD835anz ?40c to +85c 8-lead plastic dual in-line package [pdip] n-8 AD835ar ?40c to +85c 8-lead standard small outline package [soic_n] r-8 AD835ar-reel ?40c to +85c 8-lead standa rd small outline package [soic_n] r-8 AD835ar-reel7 ?40c to +85c 8-lead stan dard small outline package [soic_n] r-8 AD835arz ?40c to +85c 8-lead standard small outline package [soic_n] r-8 AD835arz-reel ?40c to +85c 8-lead stan dard small outline package [soic_n] r-8 AD835arz-reel7 ?40c to +85c 8-lead stan dard small outline package [soic_n] r-8 1 z = rohs compliant part.
AD835 rev. d | page 15 of 16 notes
AD835 rev. d | page 16 of 16 notes ?1994C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00883-0-12/10(d)

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